The present invention relates, in general, to the field of nonvolatile memory devices. More particularly, the present invention relates to a nonvolatile memory device utilizing a single transistor as the only element in the memory cell and a method for the formation of such an element incorporating a ferroelectric material as the gate dielectric thin film formed at a relatively high temperature.
Nonvolatile ferroelectric random access memory (“FeRAM”) devices represent an emerging, multibillion-dollar market. The most advanced FeRAMs utilize a 1-transistor/1 capacitor (“1T1C”) cell technology and a destructive read out (“DRO”) scheme. These devices compete with electrically erasable programmable read only memory (“EEPROMs”), battery backed static random access memory (“RAM”; “BBSRAMs”), and Flash nonvolatile memory devices.
FeRAM is a type of semiconductor memory, constructed similarly to a dynamic random access memory (“DRAM”) device, but which stores bits of data without the need for a continuous power requirement (nonvolatile characteristic). FeRAMs have gained recent interest because of the possibility that they could become the ideal memory of the future, also replacing standard mass-produced DRAM. Although the basic fundamentals of ferroelectricity were discovered in the 1920's, developments within the last fifteen years regarding the use of thin ferroelectric films may now make it practical to develop a dense memory with ideal nonvolatile memory performance characteristics. Ferroelectric materials exhibit ferroelectric behavior below a critical temperature, known as the Curie temperature. The Curie temperatures of many ferroelectric materials are above 200° C. allowing them to be used as storage elements for nonvolatile semiconductor memories.
Conventional FeRAMs operate using an array of memory cells, which contain capacitors, built of a special dielectric material (a ferroelectric) sandwiched between two conducting material (electrode) layers. The special ferroelectric material is comprised of a lattice of ions, in which one of the ions in each unit cell has two stable states on either side of the center of the unit cell along an elongated axis as shown in FIGS. 1A and 1B. When a voltage is applied across the top and bottom electrodes of a ferroelectric capacitor, the movement of these charged center ions creates a charge displacement within the dielectric. This charge displacement can be sensed as a current flowing between the electrodes of the ferroelectric capacitor. The charge displacement within a ferroelectric capacitor is often displayed as a hysteresis curve, where the polarization (or polarization charge) of the ferroelectric layer is plotted against the applied electric field (or applied voltage), as shown in FIG. 1C.
FIG. 1D shows a schematic of a conventional 1T1C memory cell. When a positive voltage is applied across a negatively polarized ferroelectric capacitor, the center ions of the unit cells switch to positively polarized states. This ion movement can be sensed as a current flow between the electrodes of the ferroelectric capacitor. When this voltage is removed, the polarization settles to the state labeled “+Q0” (See FIG. 1C). If a negative voltage is then applied across the ferroelectric capacitor, the center ions of the unit cells switch to negatively polarized states. When this voltage is removed, the polarization settles to the state labeled “−Q0”. FeRAMs offer an advantage over DRAMs because ferroelectric polarization can be retained in either state, +Q0 or −Q0, for a very long time (retention) without continuously applied power (non-volatility). Unlike other nonvolatile memory elements, ferroelectric capacitors can be switched from state to state many times (currently >1010 cycles) without wear-out (fatigue). Also, because the ferroelectric capacitors operate at a relatively low voltage, there is no need for high voltages provided by charge pumps to program (or “write”) the memory as required for certain nonvolatile memories (e.g., EEPROM and Flash). These low programming voltages ultimately allow ferroelectric memory cells to scale to smaller dimensions than Flash memory and improve radiation hardness.
Conventional techniques for processing FeRAMs require the fabrication of ferroelectric capacitors after all of the underlying complementary metal oxide semiconductor (“CMOS”) circuitry has been fabricated just prior to metalization. A typical cross section of a 1T1C cell would exhibit a ferroelectric capacitor placed on the field oxide which is connected to the associated pass transistor with a local interconnect. This presents a significant processing difficulty, because the proper ferroelectric phase has to be formed after deposition by a high temperature anneal operation, preferably in an oxygen atmosphere. When the underlying CMOS circuitry is heated to high temperatures, hydrogen is released, which degrades the ferroelectric film. Depositing the metalization interconnect layers can also produce hydrogen. Thus, a hydrogen barrier must be added to protect the ferroelectric capacitors. Also, some ferroelectric materials are very sensitive to moisture, which contamination can be formed when hydrogen is released. Finally, when relatively dense memory arrays are fabricated, planarization techniques are commonly used. Most processes require interconnect metalization to be added before the ferroelectric materials are deposited and activated. This interconnect metalization will generally not withstand the high temperatures of ferroelectric film activation. All of these problems have slowed the development of dense FeRAMs and have clouded the future for an ideal memory.
A particularly significant disadvantage of prior art 1T1C cell memories is that, under the best of circumstances, they cannot be scaled aggressively enough to compete with Flash memory since they require 2 elements per cell compared to a single element in Flash devices. With comparable design rules, a conventional FeRAM device will exhibit a cell size at least twice the cell size of Flash memory.